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general description the MAX6850 compact vacuum-fluorescent display (vfd) controller provides microprocessors with the mul- tiplex timing for 7-segment, 14-segment, or 16-segment alphanumeric vfd displays up to 96 characters and controls industry-standard, shift-register, high-voltage grid/anode vfd tube drivers. the device supports dis- play tubes using either one or two digits per grid, as well as universal displays. hardware is included to sim- plify the generation of cathode bias and filament sup- plies and to provide up to five logic outputs, including a buzzer driver. the MAX6850 provides an internal cross- point switch to match any tube-driver shift-register grid/anode order, and is compatible with both chip-in- glass and external tube drivers. the MAX6850 includes an ascii 104-character font, multiplex scan circuitry, and static ram that stores digit, cursor, and annunciator data, as well as font data for 24 user-definable characters. the display intensity can be adjusted by an internal 16-step digital bright- ness control. the device also includes separate annun- ciator and cursor control with automatic blinking, as well as a low-power shutdown mode. the MAX6850 provides timing to generate the pwm waveforms to drive the tube filament from a dc supply. the filament drive is synchronized to the display multi- plexing to eliminate beat artifacts. the MAX6850 is compatible with spi and qspi. for a 2-wire interfaced version, refer to the max6851* data sheet. applications features high-speed 26mhz spi-/qspi-/microwire- compatible serial interface 2.7v to 3.6v operation controls up to 48 grids of 7-segment, 14-segment, or 16-segment alphanumeric digits one digit and two digits per grid and universal displays supported 16-step digital brightness control built-in ascii 104-character font 24 user-definable characters up to four annunciators per grid with automatic blinking control separate cursor control with automatic blinking filament drive full-bridge waveform synthesis buzzer tone generator with single-ended or push-pull driver up to five general-purpose logic outputs 9? low-power shutdown (data retained) 16-pin qsop package MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ________________________________________________________________ maxim integrated products 1 ordering information 19-2635; rev 1; 1/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX6850aee -40 c to +125 c 16 qsop display modules retail pos displays weight and tare displays bar graph displays industrial controllers white goods professional audio equipment spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. *future product?ontact factory for availability. MAX6850 vfclk vfdout vfload vfblank osc2 din sclk osc1 cs dout sclk cs microcontroller 56pf 0.1 f gnd chip-on-glass vfd vfd supply voltage 10k ? typical application circuit pin configuration and functional diagram appear at end of data sheet.
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage (with respect to gnd) v+ .............................................................................-0.3v to +4v din, sclk, cs ......................................................-0.3v to +5.5v all other pins................................................-0.3v to (v+ + 0.3v) current v+..................................................................................200ma gnd .............................................................................-200ma phase1, phase2, port0, port1, pump................150ma vfclk, vfdout, vfload, vfblank ......................150ma continuous power dissipation (t a = +70 c) 16-pin qsop (derate at 8.34mw/ c above +70 c).....667mw operating temperature range (t min , t max ) MAX6850aee................................................-40 c to +125 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c dc electrical characteristics (typical operating circuit, v+ = 2.7v to 3.6v, t a = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units operating supply voltage v+ 2.7 3.6 v t a = t min to t max 85 shutdown supply current i shdn shutdown mode, all digital inputs at v+ or gnd t a = +25 c930 a t a = t min to t max 3.5 operating supply current i+ osc = 4mhz vfload, vfdout, vfclk, vfblank, loaded 100pf t a = +25 c 1.7 3.0 ma master clock frequency (osc internal oscillator) f osc osc1 fitted with c osc = 56pf, osc2 fitted with r osc = 10k ? ; see the typical operating circuit 4 mhz master clock frequency (osc external oscillator) osc1 overdriven with external f osc 2 8 mhz dead-clock protection frequency 200 khz osc high time t ch 50 ns osc low time t cl 50 ns fast or slow segment blink duty cycle (note 2) 49.5 50.5 % logic inputs and outputs input leakage current din, sclk, cs i ih , i il 0.2 1 a logic-high input voltage din, sclk, cs v ih 2.4 v logic-low input voltage din, sclk, cs v il 0.6 v
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units output rise and fall time phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank t rft c load = 100pf 25 ns output high-voltage phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank v oh i source = 10 ma v + - 0.6 v output low-voltage phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank v ol i sink = 10 ma 0.4 v output short-circuit source current phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank i ohsc output programmed high, output short circuit to gnd (note 2) 62 125 ma output short-circuit sink current phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank i olsc output programmed low, output short circuit to v+ (note 2) 72 125 ma 4-wire serial interface timing characteristics (figure 8) sclk clock period t cp 38.4 ns sclk pulse width high t ch 19 ns sclk pulse width low t cl 19 ns cs fall to sclk rise setup time t css 9.5 ns sclk rise to cs rise hold time t csh 5ns din setup time t ds 9.5 ns din hold time t dh 2ns minimum cs pulse high t csw 19 ns dout cascade setup time port0, port1 t csu port0 and/or port1 enabled as dout 9.5 ns vfd interface timing characteristics (figure 11) vfclk clock period t vcp (note 2) 500 2050 ns vfclk pulse width high t vch (note 2) 250 ns vfclk pulse width low t vcl (note 2) 250 ns vfclk rise to vfd load rise hold time t vcsh (note 2) 19 s vfdout setup time t vds (note 2) 50 ns vfload pulse high t vcsw (note 2) 245 ns note 1: all parameters tested at t a = +25 c. specifications over temperature are guaranteed by design. note 2: guaranteed by design. dc electrical characteristics (continued) (typical operating circuit, v+ = 2.7v to 3.6v, t a = t min to t max , unless otherwise noted.) (note 1)
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 4 _______________________________________________________________________________________ typical operating characteristics (typical operating circuit, v+ = 3.3v, t a = +25 c, unless otherwise noted.) supply current vs. supply voltage MAX6850 toc01 v+ (v) i supply (ma) 3.5 3.3 3.1 2.9 1.6 1.7 1.8 1.9 2.0 2.1 2.2 1.5 2.7 3.7 t a = -40 c t a = +125 c shutdown supply current vs. supply voltage MAX6850 toc02 v+ (v) i supply ( a) 3.5 3.3 3.1 2.9 5 15 20 35 40 45 50 0 2.7 t a = -40 c t a = +25 c t a = +125 c 10 25 30 osc1 = 0 frequency (mhz) 7 6 5 4 3 200 400 600 800 1000 1200 1400 0 28 shutdown supply current vs. external osc frequency MAX6850 toc03 i supply ( a) 80 60 40 20 0 100 output low voltage vs. i sink MAX6850 toc04 i sink (ma) v ol (v) 0.2 0.6 0.8 1.4 1.6 1.8 2.0 0 t a = -40 c 0.4 1.0 1.2 v+ = 3.3v v+ = 3.6v v+ = 2.7v 80 60 40 20 0 100 output low voltage vs. i sink MAX6850 toc05 i sink (ma) v ol (v) 0.2 0.6 0.8 1.4 1.6 1.8 2.0 0 t a = +25 c 0.4 1.0 1.2 v+ = 3.6v v+ = 2.7v v+ = 3.3v 80 60 40 20 0 100 output low voltage vs. i sink MAX6850 toc06 i sink (ma) v ol (v) 0.2 0.6 0.8 1.4 1.6 1.8 2.0 0 t a = +125 c 0.4 1.0 1.2 v+ = 3.6v v+ = 2.7v v+ = 3.3v 80 60 40 20 0 100 v in - v oh vs. i source MAX6850 toc07 i source (ma) v ol (v) 0.5 1.5 2.0 0 1.0 t a = -40 c v+ = 3.6v v+ = 2.7v v+ = 3.3v 80 60 40 20 0 100 v in - v oh vs. i source MAX6850 toc08 i source (ma) v ol (v) 0.2 0.6 0.8 1.4 1.6 1.8 2.0 0 t a = +25 c 0.4 1.0 1.2 v+ = 3.6v v+ = 2.7v v+ = 3.3v 80 60 40 20 0 100 v in - v oh vs. i source MAX6850 toc09 i source (ma) v ol (v) 0.5 1.5 2.0 0 1.0 t a = +125 c v+ = 3.6v v+ = 2.7v v+ = 3.3v
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller _______________________________________________________________________________________ 5 f osc vs. temperature MAX6850 toc10 temperature ( c) f osc (mhz) 110 95 80 65 50 35 20 5 -10 -25 0.5 1.0 1.5 2.0 2.5 0 -40 125 v+ = 2.7v v+ = 3.3v v+ = 3.6v dead-clock osc frequency vs. temperature MAX6850 toc11 temperature ( c) frequency (mhz) 110 95 80 65 50 35 20 5 -10 -25 -40 125 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0 v+ = 2.7v v+ = 3.6v v+ = 3.3v typical operating characteristics (continued) (typical operating circuit, v+ = 3.3v, t a = +25 c, unless otherwise noted.) pin description pin name function 1 vfclk serial-clock output to external driver. push-pull clock output to external display driver. on vfclk s falling edge, data is clocked out of vfdout. 2 vfdout serial-data output to external driver. push-pull data output to external display driver. 3 vfload serial-load output to external driver. push-pull load output to external display driver. rising edge is used by external display driver to load serial data into display latch. 4 vfblank display blanking output to external driver. push-pull blanking output to external display driver used for pwm intensity control. 5 pump charge-pump output and general-purpose output. user-configurable push-pull logic output can also be used as a driver for external charge pump. 6 phase1 filament drive phase1 output and general-purpose output. user-configurable push-pull logic output can also be used as a driver for external filament bridge drive. 7 phase2 filament drive phase2 output and general-purpose output. user-configurable push-pull logic output can also be used as a driver for external filament bridge drive. 8 v+ positive supply voltage. bypass v+ to gnd with a 0.1f ceramic capacitor. 9 gnd ground 10 port0 port0 general-purpose output. user-configurable push-pull logic output. 11 sclk serial-clock input. on sclk s rising edge, data shifts into the internal shift register, and data is clocked out of dout. sclk is active only while cs is low. 12 din serial-data input. data from din loads into the internal 16-bit shift register on sclk s rising edge. 13 cs chip-select input. serial data is loaded into the shift register while cs is low. the most recent 16 bits of data latch on cs s rising edge. 14 port1 port1 general-purpose output. user-configurable push-pull logic output.
MAX6850 detailed description overview of the MAX6850 the MAX6850 vfd controller generates the multiplex timing for the following vfd display types: multiplexed displays with one digit per grid, and up to 48 grids (in 48/1 mode). each grid can contain one 7-, 14-, or 16-segment character, a decimal place (dp) segment, a cursor segment, and four extra annunciator segments (figure 1). multiplexed displays with two digits per grid, and up to 48 grids (in 96/2 mode). each grid can contain two 7-, 14-, or 16-segment characters, two dp seg- ments, and two cursor segments. no annunciator segments are supported (figure 2). each digit can have a 7-, 14-, or 16-segment character, a dp segment, a cursor segment, and (for one-digit- per-grid displays only) four annunciators (figure 3). the 7, 14, or 16 segments use on-chip fonts that map the segments. the fonts comprise an ascii 104-char- acter fixed-font set, and 24 user-definable characters. the predefined characters follow the arial font, with the addition of the following common symbols: , , , , , , , and . the 24 user-definable characters are uploaded by the user into on-chip ram through the ser- ial interface and are lost when the device is powered down. as well as custom 7- and 14-segment charac- ters, the user-definable fonts can control up to 14 cus- tom segments, bar graph characters, or graphics. annunciator segments have individual, independent control, so any combination of annunciators can be lit. annunciators can be off, lit, or blink either in phase or 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 6 _______________________________________________________________________________________ pin name function 15 osc1 multiplex clock input 1. to use the internal oscillator, connect capacitor c osc from osc1 to gnd. to use the external clock, drive osc1 with a 2mhz to 8mhz cmos clock. 16 osc2 multiplex clock input 2. connect resistor r osc from osc2 to gnd. pin description (continued) grid 1 grid 2 grid 3 grid 4 grid 5 grid 6 grid 7 grid 8 grid 9 grid 10 grid 11 grid 12 grid 13 grid 14 grid 15 grid 16 figure 1. example of a one-digit-per-grid display
out of phase with the cursor. the blink-speed control is software selectable to be one or two blinks per second (osc = 4mhz). dp segments can be lit or off, but have no blink control. a dp segment is set by the same command that writes the digit s 7-, 14-, or 16-segment character. the cursor segment is controlled differently. a single register selects one digit s cursor from the entire dis- play, and that can be lit either continuously or blinking. all the other digits cursors are off. the designations of dp, cursor, and annunciator are interchangeable. for example, consider an application requiring only one dp lit at a time, but the dp needs to blink. the dp function does not have blink capability. instead, the dp segments on the display are routed (using the output map) to the cursor function. in this case, the dp segments are controlled using the cursor register. the output of the controller is a 4-wire serial stream that interfaces to industry-standard, shift-register, high-volt- age grid/anode vfd tube drivers (figure 4). this inter- face uses three outputs to transfer and latch grid and anode data into the tube drivers, and a fourth output that enables/disables the tube driver outputs (figure 6). the enable/disable control is modulated by the MAX6850 for both pwm intensity control and interdigit MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller _______________________________________________________________________________________ 7 grid 1 grid 2 grid 3 grid 4 grid 5 grid 6 grid 7 grid 8 figure 2. example of a two-digit-per-grid display c f ph mw 4 annunciator segments 14-segment character cursor segment decimal point (dp) segment figure 3. digit structure with 14-segment character, dp segment, cursor segment, and four annunciators MAX6850 vfclk vfdout vfload din sclk vfblank vfdin vfclk vfload vfblank microcontroller vfd tube driver cs dout sclk cs vfd tube grid/ anode drivers figure 4. connection of the MAX6850 to vfd driver and vfd tube
MAX6850 blanking, and disables the tube driver in shutdown. the controller multiplexes the display by enabling each grid of the vfd in turn for 100s (osc = 4mhz) with the cor- rect segment (anode) data. the data for the next grid is transferred to the tube drivers during the display time of the current grid. the controller uses an internal output map to match any tube-driver s shift-register grid/anode order, and is therefore compatible with all vfd internal chip-in-glass or external tube drivers. the MAX6850 provides five high-current output ports, which can be configured for a variety of functions. the pump output can be configured as either an 80khz (osc = 4mhz) clock intended for dc-dc converter use, the 4-wire serial interface s dout data output, or a general-purpose logic output. the phase1 and phase2 outputs can be individually configured as either 10khz pwm outputs (osc = 4mhz) intended for filament driving, blink status out- puts, or general-purpose logic outputs. the port0 and port1 outputs can be individually configured as either 625hz, 1250hz, or 2500hz clocks (osc = 4mhz) intended for buzzer driving, the 4-wire serial interface s dout data output, blink or shutdown status outputs, or general-purpose logic outputs. figure 5 shows segment labeling for 7-, 14-, and 16-segment displays. figure 6 is a block diagram of the vfd tube driver and vfd tube. display modes the MAX6850 has two display modes (table 1), select- ed by the m bit in the configuration register (table 23). the display modes trade the maximum allowable num- ber of digits (96/2 mode) against the availability of annunciator segments (48/1 mode). table 2 is the reg- ister address map. initial power-up on initial power-up, all control registers are reset, the display segment and annunciator data are cleared, intensity is set to minimum, and shutdown is enabled (table 3). 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 8 _______________________________________________________________________________________ a b c d e f g1 dp g2 hi j k l m a1 b c d1 e f g1 dp g2 hi j k l m a2 d2 a b c d e f g dp figure 5. segment labeling for 7-, 14-, and 16-segment displays serial-to-parallel shift register latches vfclk vfdin vfload vfblank o0 o0 o1 o1 o2 o2 0n-2 vfd tube driver vfd tube simplified 0n-2 0n-1 0n-1 0n 0n figure 6. block diagram of vfd tube driver and vfd tube
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller _______________________________________________________________________________________ 9 character registers the MAX6850 uses 48 character registers (48/1 mode) (table 4) or 96 character registers (96/2 mode) (table 5) to store the 7-, 14-, and 16-segment characters (table 6). each digit is represented by 1 byte of memo- ry. the data in the character registers does not control the character segments directly. instead, the register data is used to address a character generator, which stores the data of the 128-character font (table 7). the lower 7 bits of the character data (d6 to d0) select a character from the font table. the most significant bit (msb) of the register data (d7) controls the dp seg- ment of the digit; it is set to light the dp, cleared to leave it unlit. the character registers address maps are shown in table 4 (48/1 mode) and table 5 (96/2 mode). in 48/1 mode, the character registers use a single address range 0x20 to {0x20 + g}, where g is the value in the grids register (table 26). the 48/1 mode upper address limit, when g is 0x2f, is therefore 0x4f. the address range 0x50 to 0x7f is used for annunciator data in 48/1 mode. in 96/2 mode, the character registers use two address ranges. the first row s address range is 0x20 to {0x20 + g}. the second row s address range is 0x50 to {0x50 + g}. therefore, in 96/2 mode, the character reg- isters are only one contiguous memory range when a 48-grid display is used. display mode maximum no. of digits maximum no. of annunciators maximum no. of grids digits covered by each grid 48/1 mode 48 digits, each with a dp segment and a cursor segment 4 per digit 1 digit per grid 96/2 mode 96 digits, each with a dp segment and a cursor segment none 48 grids 2 digits per grid table 1. display modes command address register d15 d14 d13 d12 d11 d10 d9 d8 hex code no-op r/ w 0000000 0x00 vfblank polarity r/ w 0000001 0x01 intensity r/ w 0000010 0x02 grids r/ w 0000011 0x03 configuration r/ w 0000100 0x04 user-defined fonts r/ w 0000101 0x05 output map r/ w 0000110 0x06 display test and device id r/ w 0000111 0x07 pump register r/ w 0001000 0x08 filament duty cycle r/ w 0001001 0x09 phase1 r/ w 0001010 0x0a phase2 r/ w 0001011 0x0b port0 r/ w 0001100 0x0c port1 r/ w 0001101 0x0d shift limit r/ w 0001110 0x0e cursor r/ w 0001111 0x0f factory reserved. do not write to register. x 0010000 0x10 table 2. register address map
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 10 ______________________________________________________________________________________ character generator font mapping the font comprises 104 characters in rom, and 24 user-definable characters. the selection from the total of 128 characters is represented by the lower 7 bits of the 8-bit digit registers. the msb, shown as x in the rom maps (tables 7 and 8), controls the dp segment of the digit; it is set to light the dp. there are two font maps stored in the MAX6850. one font map covers 14-segment displays (table 8), and the other suits 16-segment displays (table 7). the f bit in the configuration register (table 20) selects between the two font maps. the f bit may be set either high or low for 7-segment displays; 7-segment displays use a subset of the 14- or 16-segment display described in two font maps (figure 7). register data register power-up condition command address d7 d6 d5 d4 d3 d2 d1 d0 vfblank polarity vfblank is high to disable the display 0x01 x x x x x x 0 0 intensity 1/16 (min on) 0x02 x x x x 0000 grids display has 1 grid 0x03 x x 0 00000 configuration shutdown enabled, configuration unlocked 0x04 1 0 0 00000 user-defined font address pointer address 0x80; pointing to the first user-defined font location 0x05 1 0 0 00000 user-defined fonts predefined for hex fonts see table 11 for power-up patterns. output map pointer address 0x80; pointing to the first entry address 0x06 1 0 0 00000 output map data predefined for 40-digit display see table 32 for power-up patterns. display test normal operation 0x07 x x x xxxx0 pump general-purpose output, logic 0x08 0 0 0 00000 filament duty cycle minimum duty cycle 0x09 0 0 0 00001 phase1 general-purpose output, logic 0x0a 0 0 0 00000 phase2 general-purpose output, logic 0x0b 0 0 0 00000 port0 general-purpose output, logic 0x0c 0 0 0 00000 port1 general-purpose output, logic 0x0d 0 0 0 00001 shift limit 1 output bit 0x0e x 0 0 00001 cursor off 0x0f 0 1 1 00000 character and annunciator data clear 0x20 0 0 0 00000 up to up to character and annunciator data clear 0x7f 0 0 0 00000 table 3. initial power-up register status maps to 7 segment 14/16 segment dp dp a g d ec fb a/a1 g1 d/d2 ec fb figure 7. 14- and 16-segment fonts map a subset of their 14 or 16 segments to a 7-segment digit
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 11 the character map follows the arial font for 96 charac- ters in the x0100000 through x1111111 range. the first 32 characters map the 24 user-definable positions (ram00 to ram23), plus eight extra common charac- ters in rom. user-defined fonts the 24 user-definable characters are represented by 48 entries of 7-bit data, two entries per character, and are stored in the MAX6850 s internal ram. command address register d15 d14 d13 d12 d11 d10 d9 d8 hex code digit 0 character r/ w 0 1 0 0 0 0 0 0x20 digit 1 character r/ w 0 1 0 0 0 0 1 0x21 digit 2 character r/ w 0 1 0 0 0 1 0 0x22 up to digit 45 character r/ w 1 0 0 1 1 0 1 0x4d digit 46 character r/ w 1 0 0 1 1 1 0 0x4e digit 47 character r/ w 1 0 0 1 1 1 1 0x4f digit 0 annunciators r/ w 1 0 1 0 0 0 0 0x50 digit 1 annunciators r/ w 1 0 1 0 0 0 1 0x51 digit 2 annunciators r/ w 1 0 1 0 0 1 0 0x52 up to digit 45 annunciators r/ w 1 1 1 1 1 0 1 0x7d digit 46 annunciators r/ w 1 1 1 1 1 1 0 0x7e digit 47 annunciators r/ w 1 1 1 1 1 1 1 0x7f table 4. character and annunciator register address map in 48/1 mode table 5. character register address map in 96/2 mode command address register d15 d14 d13 d12 d11 d10 d9 d8 hex code digit 0 character, 1st row r/ w 0 1 0 0 0 0 0 0x20 digit 1 character, 1st row r/ w 0 1 0 0 0 0 1 0x21 digit 2 character, 1st row r/ w 0 1 0 0 0 1 0 0x22 up to r/ w digit 45 character, 1st row r/ w 1 0 0 1 1 0 1 0x4d digit 46 character, 1st row r/ w 1 0 0 1 1 1 0 0x4e digit 47 character, 1st row r/ w 1 0 0 1 1 1 1 0x4f digit 0 character, 2nd row r/ w 1 0 1 0 0 0 0 0x50 digit 1 character, 2nd row r/ w 1 0 1 0 0 0 1 0x51 digit 2 character, 2nd row r/ w 1 0 1 0 0 1 0 0x52 up to r/ w digit 45 character, 2nd row r/ w 1 1 1 1 1 0 1 0x7d digit 46 character, 2nd row r/ w 1 1 1 1 1 1 0 0x7e digit 47 character, 2nd row r/ w 1 1 1 1 1 1 1 0x7f
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 12 ______________________________________________________________________________________ the user-definable characters are preloaded on power- up with 24 fonts. these fonts are intended to be useful for 7-segment displays, and include the hexadecimal set for the first 16 characters, plus eight other useful segment combinations. table 12 shows how the 14-segment and 16-segment fonts map to 7-segment displays. the 48 user-definable font data entries are written and read through a single register, address 0x05. an autoincrementing font address pointer in the MAX6850 indirectly accesses the font data. the font address pointer can be written, setting one of 48 addresses between 0x00 and 0x2f, but cannot be read back. the font data is written to and read from the MAX6850 indi- rectly, using this font address pointer. unused font locations can be used as general-purpose scratch ram, bearing in mind that the font registers are only 7 bits wide, not 8. table 9 shows how to use the single user-defined font register 0x05 to set the font address pointer, write font data, and read font data. a read action always returns font data from the font address pointer position. a write action sets the 7-bit font address pointer if the msb is set, or writes 7-bit font data to the font address pointer position if the msb is clear. the font address pointer autoincrements after a valid access to the user-definable font data. autoincrementing allows the 48-font data entries to be written and read back very quickly because the font pointer address needs be set only once. after the last data location 0x2f has been written, further font data entries are ignored until the font address pointer is reset. if the font address point- er is set to an out-of-range address by writing data in the 0xb0 to 0xff range, then address 0x80 is set instead (table 10). table 11 shows the user-definable font pointer ad- dresses. table 12 shows bit/segment mapping for user-defined fonts when applied to 7-, 14-, or 16-segment digits. table 13 illustrates how to set the font address pointer to a value within the acceptable range. d7 is set (1) to denote that the user is writing the font address pointer. if the user attempts to set the font address to one of the out-of-range addresses by writing data in range 0xb0 to 0xff, then address 0x00 is set instead. the font address pointer autoincrements from address (the last user font location) to point to address 0x00 (the first user font location). thus, the font address pointer autoincrements indefinitely through font ram. cursor register the cursor register controls the behavior of the cursor segments (table 14). the MAX6850 controls 48 cursors in 48/1 mode, and 96 cursors in 96/2 mode. the cursor register selects one digit s cursor to be lit either contin- uously or blinking. all the other digits cursors are off. the 7 least significant bits (lsbs) of the cursor register identify the cursor position. the msb is clear for the cursor to be on continuously, and set for the cursor to be lit only during the first half of each blink period. the valid cursor position address range is contiguous: 0 to 47 (0x00 to 0x2f) for the first row, and 48 to 95 (0x30 to 0x5f) for the 2nd row. if the cursor register is programmed with an out-of-range value of 95 to 127 (0x60 to 0x7f), then all cursors are off. annunciator registers the annunciator registers are organized in bytes, with each segment of each grid being represented by 2 bits. thus, the four annunciators segments allowed for each grid are represented by exactly 1 byte (table 15). annunciators are only available in 48/1 mode. the annunciator address map is shown in table 4. configuration register the configuration register is used to enter and exit shut- down, lock the key vfd configuration settings, select the blink rate, globally clear the digit and annunciator data, reset the blink timing, and select between 48/1 and 96/2 display modes (table 16). register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 writing character data to use font map data with dp segment unlit 0x20 to 0x4f (48/1 mode) 0x20 to 0x7f (96/2 mode) 0 writing character data to use font map data with dp segment lit 0x20 to 0x4f (48/1 mode) 0x20 to 0x7f (96/2 mode) 1 bits d6 to d0 select font characters 0 to 127 table 6. character registers format
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 13 x000 x010 x011 x100 x101 x110 x111 x001 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 msb lsb ram00 ram01 ram02 ram03 ram04 ram05 ram06 ram07 ram08 ram09 ram0a ram0b ram0c ram0d ram0e ram0f ram10 ram11 ram12 ram13 ram14 ram15 ram16 ram17 table 7. 16-segment display font map x000 x010 x011 x100 x101 x110 x111 x001 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 msb lsb ram00 ram01 ram02 ram03 ram04 ram05 ram06 ram07 ram08 ram09 ram0a ram0b ram0c ram0d ram0e ram0f ram10 ram11 ram12 ram13 ram14 ram15 ram16 ram17 table 8. 14-segment display font map
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 14 ______________________________________________________________________________________ command address register data read or write function 0x85 0x00 0x7f read read 7-bit user-definable font data entry from current font address. msb of the register data is clear. font address pointer is incremented after the read. 0x05 0x00 0x7f write write 7-bit user-definable font data entry to current font address. font address pointer is incremented after the write. 0x05 0x80 0xff write write font address pointer with the register data. table 9. memory mapping of user-defined font register 0x05 font pointer address action 0x80 to 0xae valid range to set the font address pointer. pointer autoincrements after a font data read or write, while pointer address remains in this range. 0xaf further font data is ignored after a font data read or write to this pointer address. 0xb0 to 0xff invalid range to set the font address pointer. pointer is set to 0x80. table 10. font pointer address behavior register data font character power-up default ( bin ) power-up character command address register data d7 d6 d5 d4 d3 d2 d1 d0 ram00 byte 0 111 1110 7-segment 0 0x05 0x80 1 0 000000 ram00 byte 1 000 0000 0x05 0x81 1 0 000001 ram01 byte 0 011 0000 7-segment 1 0x05 0x82 1 0 000010 ram01 byte 1 000 0000 0x05 0x83 1 0 000011 ram02 byte 0 110 1101 7-segment 2 0x05 0x84 1 0 000100 ram02 byte 1 000 0000 0x05 0x85 1 0 000101 ram03 byte 0 111 1001 7-segment 3 0x05 0x86 1 0 000110 ram03 byte 1 000 0000 0x05 0x87 1 0 000111 ram04 byte 0 011 0011 7-segment 4 0x05 0x88 1 0 001000 ram04 byte 1 000 0000 0x05 0x89 1 0 001001 ram05 byte 0 101 1011 7-segment 5 0x05 0x8a 1 0 001010 ram05 byte 1 000 0000 0x05 0x8b 1 0 001011 ram06 byte 0 101 1111 7-segment 6 0x05 0x8c 1 0 001100 ram06 byte 1 000 0000 0x05 0x8d 1 0 001101 ram07 byte 0 111 0000 7-segment 7 0x05 0x8e 1 0 001110 ram07 byte 1 000 0000 0x05 0x8f 1 0 001111 ram08 byte 0 111 1111 7-segment 8 0x05 0x90 1 0 010000 ram08 byte 1 000 0000 0x05 0x91 1 0 010001 ram09 byte 0 111 1011 7-segment 9 0x05 0x92 1 0 010010 ram09 byte 1 000 0000 0x05 0x93 1 0 010011 ram10 byte 0 111 0111 7-segment a 0x05 0x94 1 0 010100 table 11. user-definable font pointer addresses
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 15 shutdown mode (s data bit d0) format the s bit in the configuration register selects shutdown or normal operation (table 17). the display driver can be programmed while in shutdown mode, and shut- down mode is overridden when in display test mode. for normal operation, set s bit to 1. when the MAX6850 is in shutdown mode, the multiplex oscillator is halted at the end of the current 100s multi- plex period (osc = 4mhz), and the vfblank output is used to disable the vfd tube driver. data in the digit and other control registers remain unaltered. if the pump output is configured as a square-wave clock, then the pump output is forced low for the dura- tion of shutdown, and the square-wave clock restored when the MAX6850 comes out of shutdown. if the phase1 output or phase2 output is configured as a filament driver, then that output is forced low for the duration of shutdown and the filament drive waveforms restored when the MAX6850 comes out of shutdown. when the MAX6850 comes out of shutdown, the exter- nal vfd tube driver is presumed to contain invalid data. the vfblank output is used to disable the vfd tube driver for the first multiplex cycle after exiting shutdown, clearing any invalid data. the next multiplex cycle uses newly sent valid data. register data font character power-up default ( bin ) power-up character command address register data d7 d6 d5 d4 d3 d2 d1 d0 ram10 byte 1 000 0000 0x05 0x95 1 0 010101 ram11 byte 0 001 1111 7-segment b 0x05 0x96 1 0 010110 ram11 byte 1 000 0000 0x05 0x97 1 0 010111 ram12 byte 0 100 1110 7-segment c 0x05 0x98 1 0 011000 ram12 byte 1 000 0000 0x05 0x99 1 0 011001 ram13 byte 0 011 1101 7-segment d 0x05 0x9a 1 0 011010 ram13 byte 1 000 0000 0x05 0x9b 1 0 011011 ram14 byte 0 100 1111 7-segment e 0x05 0x9c 1 0 011100 ram14 byte 1 000 0000 0x05 0x9d 1 0 011101 ram15 byte 0 100 0111 7-segment f 0x05 0x9e 1 0 011110 ram15 byte 1 000 0000 0x05 0x9f 1 0 011111 ram16 byte 0 000 1101 7-segment c 0x05 0xa0 1 0 100000 ram16 byte 1 000 0000 0x05 0xa1 1 0 100001 ram17 byte 0 001 0101 7-segment n 0x05 0xa2 1 0 100010 ram17 byte 1 000 0000 0x05 0xa3 1 0 100011 ram18 byte 0 111 0110 7-segment n 0x05 0xa4 1 0 100100 ram18 byte 1 000 0000 0x05 0xa5 1 0 100101 ram19 byte 0 001 1101 7-segment o 0x05 0xa6 1 0 100110 ram19 byte 1 000 0000 0x05 0xa7 1 0 100111 ram20 byte 0 000 0101 7-segment r 0x05 0xa8 1 0 101000 ram20 byte 1 000 0000 0x05 0xa9 1 0 101001 ram21 byte 0 100 1111 7-segment t 0x05 0xaa 1 0 101010 ram21 byte 1 000 0000 0x05 0xab 1 0 101011 ram22 byte 0 001 1100 7-segment u 0x05 0xac 1 0 101100 ram22 byte 1 000 0000 0x05 0xad 1 0 101101 ram23 byte 0 011 1011 7-segment y 0x05 0xae 1 0 101110 ram23 byte 1 000 0000 0x05 0xaf 1 0 101111 table 11. user-definable font pointer addresses (continued)
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 16 ______________________________________________________________________________________ bit/segment mapping for user-definable fonts when applied to 7-segment digits font byte bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ramxx byte 0 7-seg a 7-seg b 7-seg c 7-seg d 7-seg e 7-seg f 7-seg g ramxx byte 1 no action no action no action no action no action no action no action bit/segment mapping for user-definable fonts when applied to 14-segment digits font byte bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ramxx byte 0 7-seg a 7-seg b 7-seg c 7-seg d 7-seg e 7-seg f 7-seg g1 ramxx byte 1 14-seg g2 14-seg h 14-seg i 14-seg j 14-seg k 14-seg l 14-seg m bit/segment mapping for user-definable fonts when applied to 16-segment digits font byte bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ramxx byte 0 7-seg a1 7-seg b 7-seg c 7-seg d2 7-seg e 7-seg f 7-seg g1 ramxx byte 1 14-seg g2 14-seg h 14-seg i 14-seg j 14-seg k 14-seg l 14-seg m table 12. user-definable character mapping register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 set font address to minimum (zero) with data 128 or 0x80. (note that this address is set as power-up default.) 0x05 1 0000000 set font address to maximum (47 or 0x2f) with data 175 or 0xaf. 0x05 1 0101111 set font address out of range (48 or 0x30) with data 176 or 0xb0 results in font address pointer being set to zero. 0x05 1 1111000 up to up to set font address out of range (127 or 0x7f) with data 255 or 0xff results in font address pointer being set to zero. 0x05 1 1111111 read font address. 0x85 0 font address; has value 0x00 to 0xa7 table 13. setting a font character to ram register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 cursor register. 0x0f blink cursor position 1st row digit 0's cursor is lit continuously. 0x0f 0 0 0 0 0 0 0 0 1st row digit 0's cursor is lit only for the first half of each blink period. 0x0f 1 0 0 0 0 0 0 0 up to up to 2nd row digit 47's cursor is lit continuously. 0x0f 0 1 0 1 1 1 1 1 2nd row digit 47's cursor is lit only for the first half of each blink period. 0x0f 1 1 0 1 1 1 1 1 no cursor is lit. 0x0f x 1 1 x x x x x table 14. cursor register format
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 17 register data annunciator byte d7 d6 d5 d4 d3 d2 d1 d0 bit allocations annunciator a4 annunciator a3 annunciator a2 annunciator a1 annunciator a1 is off. xxxxxx00 annunciator a1 is lit only for the first half of each blink period. xxxxxx01 annunciator a1 is lit only for the second half of each blink period. xxxxxx10 annunciator a1 is lit continuously. xxxxxx11 annunciator a2 is off. xxxx00xx annunciator a2 is lit only for the first half of each blink period. xxxx01xx annunciator a2 is lit only for the second half of each blink period. xxxx10xx annunciator a2 is lit continuously. xxxx11xx annunciator a3 is off. x x 0 0 x x x x annunciator a3 is lit only for the first half of each blink period. xx01xxxx annunciator a3 is lit only for the second half of each blink period. xx10xxxx annunciator a3 is lit continuously. x x 1 1 x x x x annunciator a4 is off. 0 0 x x x x x x annunciator a4 is lit only for the first half of each blink period. 01xxxxxx annunciator a4 is lit only for the second half of each blink period. 10xxxxxx annunciator a4 is lit continuously. 1 1 x x x x x x table 15. annunciator registers format register data mode d7 d6 d5 d4 d3 d2 d1 d0 configuration register pmr t fb l s table 16. configuration register format register data mode d7 d6 d5 d4 d3 d2 d1 d0 unlocked p m r t f b 0 s locked p m r t f b 1 s table 18. configuration lock (l data bit d1) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 shutdown p m r t f b l 0 normal operation p m r t f b l 1 table 17. shutdown control (s data bit d0) format
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 18 ______________________________________________________________________________________ configuration lock (l data bit d1) format the configuration lock register is a safety feature to reduce the risk of the vfd configuration settings being inadvertently changed due to spurious writes if soft- ware fails. when set, the shift-limit register (0x0e), grids register (0x03), and output map data (0x06) can be read but cannot be written. the output map data point- er itself may be written in order to allow the output map data to be read back (table 18). blink rate selection (b data bit d2) format the b bit in the configuration register selects the blink rate of the cursor and annunciator segments. this is the speed that the segments blink on and off when blinking is selected for these segments. the frequency of the multiplex clock osc and the setting of the b bit (table 19) determine the blink rate. font selection (f data bit d3) format the f bit (table 20) selects the internal font map between 14-segment and 16-segment displays. if a 7- segment display is used, the f bit can be either set or cleared. global blink timing synchronization (t data bit d4) format setting the t bit in multiple MAX6850s at the same time (or in quick succession) synchronizes the blink timing across all the devices (table 21). the display multiplex- ing sequence is also reset, which can give rise to a one-time display flicker when the register is written. global clear digit data (r data bit d5) format when the r bit (table 22) is set, the segment and annunciator data are cleared. display mode (m data bit d6) format the m bit (table 23) selects the display modes (table 1). the display modes trade the maximum allowable number of digits (mode 96/2) against the availability of annunciator segments (mode 48/1). blink phase readback (p data bit d7) format when the configuration register is read, the p bit reflects the blink phase at that time (table 24). microcontroller 4-wire serial interface the MAX6850 communicates through an spi-compati- ble 4-wire serial interface (figure 8). the interface has three inputs, clock (sclk), chip select ( cs ), data in (din), and output data out (dout). cs must be low to clock data into or out of the device, and din must be stable when sampled on the rising edge of sclk. dout is not a specific pin, but instead, any of the pump, port0, or port1 outputs can be configured to be dout. dout is stable on the rising edge of sclk. while the spi protocol expects dout to be high impedance when the MAX6850 is not being accessed, dout on the MAX6850 is never high impedance. sclk and din can be used to transmit data to other peripher- als. the MAX6850 ignores all activity on sclk and din except when cs is low. control and operation using the 4-wire interface controlling the MAX6850 requires sending a 16-bit word. the first byte, d15 through d8, is the command address, and the second byte, d7 through d0, is the data to be written to the command address (table 25). connecting multiple MAX6850s to the 4-wire bus daisy-chain multiple MAX6850s by connecting the dout of one device to the din of the next, and driving sclk and cs lines in parallel. data at din propagates through the internal shift registers and appears at dout 15.5 clock cycles later, clocked out on the rising edge of sclk. when sending commands to daisy- chained MAX6850s, all devices are accessed at the same time. an access requires (16 x n) clock cycles, where n is the number of MAX6850s connected togeth- er. to update just one device in a daisy-chain, send the no-op command (0x00) to the others. care must be taken on power-up when daisy-chaining the serial inter- face in this manner. configure each MAX6850 s port0 or port1 outputs, in turn, to act as dout before data propagates through it. for this reason, port0 is the preferred output to configure as dout because its out- put on power-up is low. this means that a daisy- chained din input taking data from an uninitialized port0 output clocks in 16 logic zeros, which is the safe no-op instruction. register data mode d7 d6 d5 d4 d3 d2 d1 d0 slow blinking (cursor and annunciators blink on for 1s, off for 1s, for osc = 4mhz) p m r t f 0 l s fast blinking (cursor and annunciators blink on for 0.5s, off for 0.5s, for osc = 4mhz) p m r t f 1 l s table 19. blink rate selection (b data bit d2) format
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 19 register data mode d7 d6 d5 d4 d3 d2 d1 d0 14- and 7-segment fonts p m r t 0 b l s 16- and 7-segment fonts p m r t 1 b l s table 20. font selection (f data bit d3) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 blink timing counters are unaffected. p m r 0 f b l s blink timing counters are cleared on the rising edge of cs .pmr1fbls table 21. global blink timing synchronization (t data bit d4) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 segment and annunciator data are unaffected. p m 0 t f b l s segment and annunciator data (address range 0x20 to 0x7f) are cleared on the rising edge of cs . pm1tfbls table 22. global clear digit data (r data bit d5) format register data mode display type d7 d6 d5 d4 d3 d2 d1 d0 48/1 up to 48 digits, 1 digit per grid p 0 r t f b l s 96/2 up to 96 digits, 2 digits per grid p 1 r t f b l s table 23. display mode (m data bit d6) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 p1 blink phase 0 m r t f b l s p0 blink phase 1 m r t f b l s table 24. blink phase readback (p data bit d7) format d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/ w command address msb register data lsb table 25. serial-data format (16 bits)
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 20 ______________________________________________________________________________________ writing device registers the MAX6850 contains a 16-bit shift register into which din is clocked on the rising edge of sclk, when cs is low. when cs is high, transitions on sclk have no effect. when cs goes high, the 16 bits in the shift regis- ter are parallel loaded into a 16-bit latch. the 16 bits in the latch are then decoded and executed. the MAX6850 is written to using the following sequence: 1) take sclk low. 2) take cs low. this enables the internal 16-bit shift register. 3) clock 16 bits of data into din, d15 first to d0 last, observing the setup and hold times. bit d15 is low, indicating a write command. 4) take cs high (while sclk is still high after clocking in the last data bit). 5) take sclk low. figure 9 shows a write operation when 16 bits are transmitted. if fewer or greater than 16 bits are clocked into the MAX6850 between taking cs low and taking cs high again, the MAX6850 stores the last 16 bits received, including the previous transmission(s). the general case is when n bits (where n > 16) are transmitted to the MAX6850. the last bits comprising bits {n-15} to {n} are retained and are parallel loaded into the 16-bit latch as bits d15 to d0, respectively (figure 10). reading device registers any register data within the MAX6850 may be read by sending a logic high to bit d15. the sequence is: 1) take sclk low. 2) take cs low. this enables the internal 16-bit shift register. cs clk din d15 = 0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dout d15 = 0 figure 9. 16-bit write transmission to the MAX6850 t css t cl t ch t cp t csh t csw t ds t dh dn sclk din cs dn-1 d1 d0 d15 t csu dout figure 8. 4-wire serial interface timing diagram
3) clock 16 bits of data into din, d15 first to d0 last, observing the setup and hold times. bit d15 is high, indicating a read command, and bits d14 through d8 contain the address of the register to read. bits d7 to d0 contain dummy data, which is discarded. 4) take cs high. positions d7 through d0 in the shift register are now loaded with the data in the register addressed by bits d15 through d8. 5) take sclk low. 6) issue another read or write command (which can be no-op), and examine the bit stream at dout; the first 8 bits contain the address of the register that was read ( note: the msb, which was transmitted as a 1 for a read command, may read back either as a 1 or a zero). the second 8 bits are the contents of the register addressed by bits d14 through d8 in step 3. vfd driver serial interface the vfd driver interface on the MAX6850 is a serial interface using three output pins, vfload, vfclk, and vfdout (figure 11) to drive industry-standard, shift- register, high-voltage grid/anode vfd tube drivers (figures 4 and 6). the speed of vfclk is 1mhz when osc is 4mhz. the maximum speed of vfclk is 2mhz when osc is 8mhz. this interface is used to transfer display data from the MAX6850 to the vfd tube driver. the serial interface bit stream output is programmable up to 84 bits, which are labeled dd0 dd83. the functions of the three interface pins are as follows: vfclk is the serial clock output, which shifts data on its falling edge from the MAX6850 s 84-bit output shift register to vfload. vfdout is the serial data output. the data changes on vfclk s falling edge, and is stable when it is sampled by the display driver on the rising edge of vfclk. vfload is the latch-load output. vfload is high to transfer data from the display tube driver s shift register to the display driver s output latch (transparent mode), and low to retain that data in the display driver s output latch. a fourth output pin, vfblank, provides gating control of the tube driver. vfblank can be configured to be either high or low using the vblank polarity register (table 28) to enable the vfd tube driver. in the default condition, vfblank is high to disable the vfd tube dri- ver, which is expected to force its driver outputs low to blank the display without altering the contents of its out- MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 21 cs clk din bit 1 bit 2 n-9 n-8 n-7 n-6 n-5 n-4 n-3 n-2 dout n-15 = 0 n-15 = 0 n-14 n-13 n-12 n-11 n-10 n-1 n-31 n-30 n-29 n-28 n-27 n-26 n-25 n-24 n-23 n-22 n-21 n-20 n-19 n-18 n-17 n-16 n figure 10. transmission of more than 16 bits to the MAX6850 t vcl t vds t vch t vcp t vcsh t vcsw vfclk vfload m (m is value in shift-limit register) vfdout dd0 dd1 m-1 figure 11. vfd interface timing diagram
MAX6850 put latches. in the default condition, vfblank is low to enable its vfd tube driver outputs to follow the state of the vfd tube driver s output latches. the vfblank out- put is used for pwm intensity control and to disable the vfd tube driver in shutdown. multiplex architecture the multiplex engine transmits grid and anode control data to the external vfd driver using vfclk, vfdout, and vfload. the number of data bits m transmitted is set by the user in the shift-limit register (table 30). figure 12 is the vfd multiplex timing diagram. the essential rules for multiplex action are as follows: the external vfd driver s data latch contains the data for the current grid being displayed. the vfblank input is controlled to provide the pwm intensity control. the vfclk and vfdout outputs are used to fill the external vfd driver s shift register with the multiplex data for the next grid, during the multiplex timeslot for the current grid. the vfload output loads the new grid-anode data pattern at the start of its multiplex cycle. 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 22 ______________________________________________________________________________________ register data grids command address d7 d6 d5 d4 d3 d2 d1 d0 hex code display has 1 grid: g0 (always) 0x03 0 0 0 0 0 0 0 0 0x00 display has 2 grids: g0 and g1 0x03 0 0 0 0 0 0 0 1 0x01 display has 3 grids: g0 to g2 0x03 0 0 0 0 0 0 1 0 0x02 display has 4 grids: g0 to g3 0x03 0 0 0 0 0 0 1 1 0x03 up to 0x03 0 0 display has 45 grids: g0 to g44 0x03 0 0 1 0 1 1 0 0 0x2c display has 46 grids: g0 to g45 0x03 0 0 1 0 1 1 0 1 0x2d display has 47 grids: g0 to g46 0x03 0 0 1 0 1 1 1 0 0x2e display has 48 grids: g0 to g47 0x03 0 0 1 0 1 1 1 1 0x2f table 26. grids register format vfclk vfdout vfload dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 dd8 dd9 dd10 m-4 m-3 m-2 m-1 m (m is value in shift-limit register) grid 1's data, sent during grid 0's timeslot grid 0's 100 s multiplex timeslot one complete multiplex cycle around n grids (osc = 4mhz) start of next cycle 1.25 s 1.25 s 1 s1 s 100 s timeslot grid 0 100 s timeslot grid 1 100 s timeslot grid n-4 100 s timeslot grid n-3 100 s timeslot grid n-2 100 s timeslot grid n-1 100 s timeslot grid 0 figure 12. vfd multiplex timing diagram
grids register the grids register sets how many grids are multiplexed from 1 to 48 (table 26). when the grids register is written, the external vfd tube driver is presumed to contain invalid data. the vfblank output is used to disable the vfd tube driver for the first multiplex cycle after exiting shutdown, clear- ing any invalid data. the next multiplex cycle uses newly sent, valid data. if the grids register is written with an out-of-range value of 0x30 to 0xff, then the value 0x2f is stored instead. intensity register digital control of display brightness is provided by pulse-width modulation of the tube blanking time, which is controlled by the lower nibble of the intensity register (table 27). the modulator scales the vfblank output in 15 steps from a minimum of 1/16 up to 15/16 of each grid s multiplex period. figure 13 shows the modulator behavior when the vfblank polarity register is set to 0x00 (table 28), so vfblank is high to disable (blank) the display. the minimum off-time period of a 1/16 multiplex period (6.25s with osc = 4mhz) is always at the start of the multiplex cycle. this allows time for slow display drivers to turn off, and slow display phosphors time to decay between grids. thus, image ghosting is avoided. if a display has very slow phosphor, then the allowed decay time can be doubled by not using a 15/16 duty cycle. vfblank polarity register the vfblank polarity register sets the active level of the vfblank output pin (table 28). no-op register a write to the no-op register is ignored. display-test and device id register writing the display-test and device id register switches the drivers between one of two modes: normal and dis- play test. display-test mode turns all segments and MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 23 register data duty cycle vfblank behavior (osc = 4mhz) command address d7 d6 d5 d4 d3 d2 d1 d0 hex code 1/16 (min on) high for 6.25s, low for 6.25s, high for 87.5s 0x02 xxxx 0000 0xx0 2/16 high for 6.25s, low for 12.5s, high for 81.25s 0x02 xxxx 0001 0xx1 3/16 high for 6.25s, low for 18.75s, high for 75s 0x02 xxxx 0010 0xx2 4/16 high for 6.25s, low for 25s, high for 68.75s 0x02 xxxx 0011 0xx3 5/16 high for 6.25s, low for 31.25s, high for 62.5s 0x02 xxxx 0100 0xx4 6/16 high for 6.25s, low for 37.5s, high for 56.25s 0x02 xxxx 0101 0xx5 7/16 high for 6.25s, low for 43.75s, high for 50s 0x02 xxxx 0110 0xx6 8/16 high for 6.25s, low for 50s, high for 43.75s 0x02 xxxx 0111 0xx7 9/16 high for 6.25s, low for 56.25s, high for 37.5s 0x02 xxxx 1000 0xx8 10/16 high for 6.25s, low for 62.5s, high for 31.25s 0x02 xxxx 1001 0xx9 11/16 high for 6.25s, low for 68.75s, high for 25s 0x02 xxxx 1010 0xxa 12/16 high for 6.25s, low for 75s, high for 18.75s 0x02 xxxx 1011 0xxb 13/16 high for 6.25s, low for 81.25s, high for 12.5s 0x02 xxxx 1100 0xxc 14/16 high for 6.25s, low for 87.5s, high for 6.25s 0x02 xxxx 1101 0xxd 15/16 high for 6.25s, low for 93.75s 0x02 xxxx 1110 0xxe 15/16 (max on) high for 6.25s, low for 93.75s 0x02 xxxx 1111 0xxf table 27. intensity register format
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 24 ______________________________________________________________________________________ grid 0's 100 s multiplex timeslot one complete multiplex cycle around n grids (osc = 4mhz) start of next cycle 100 s timeslot grid 0 100 s timeslot grid 1 100 s timeslot grid n-4 100 s timeslot grid n-3 100 s timeslot grid n-2 100 s timeslot grid n-1 100 s timeslot grid 0 minimum 6.25 s interdigit blanking interval (osc = 4mhz) vfblank 1/16th (min on) 2/16th 3/16th 4/16th 5/16th 6/16th 7/16th 8/16th 9/16th 10/16th 11/16th 12/16th 13/16th 14/16th 15/16th 15/16th (max on) figure 13. blank and intensity timing diagram
annunciators on and sets the duty cycle to 7/16 (half- power) (table 29). reading the display-test and device id register returns the MAX6850 device id 0b0000 010 that identifies the driver type, plus the display-test status in the lsb. output shift-limit register the output serial interface is used to transfer display data from the MAX6850 to the display driver. the serial interface bit-stream output length is programmable up to 84 bits, which are labeled dd0 dd83. set the num- ber of bits with the shift-limit register, address 0x0e. if the shift-limit register is written with an out-of-range value 0x54 to 0xff, then the value 0x53 is stored instead. table 30 shows the shift-limit register. output map the output map comprises 84 words of 7-bit ram. the output map data should be written when the MAX6850 is configured after power-up. table 31 shows the out- put map ram codes. the output map is an indirect addressing reference table. it translates bit position in the output shift register (valid range: from zero to the value in shift-limit register 0e, which has a maximum of 83) to bit function. any output shift-register bit position may be set to any grid character segment, dp segment, annunciator segment, or cursor segment. the power-up default pattern for output map ram maps a 40-digit, two-digits-per-grid display with dps and cursors (table 32). if the user selects an unused map ram entry (88 127) for an output shift-register position, then the correspond- ing output bit is always low (segment or grid off). when selecting an invalid map ram entry (for example, codes 48 to 83 to select annunciators in 96/2 mode, which does not support annunciators), the correspond- ing output bit is always low (segment or grid off). if the map ram entry corresponds to a nonexistent font segment (no action in table 32) when the digit data is processed through the character font, then the result again is zero (segment or grid off). the output map data is indirectly accessed by an autoincrementing output map address pointer in the MAX6850 at address 0x06. the output map address pointer can be written (i.e., set to an address between 0x00 and 0x53) but cannot be read back. the output map data is written and read back through the output map address pointer. MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 25 register data grids command address d7 d6 d5 d4 d3 d2 d1 d0 hex code vfblank is high to disable the display. 0x01 x x x x x x 0 0 0xx0 vfblank is low to disable the display. 0x01 x x x x x x 1 0 0xx2 table 28. vfblank polarity register format register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 normal operation 0x07 x x x xxxx0 display test 0x07 x x x xxxx1 read MAX6850 device id and display test status 0x87 0 0 0 0010dt table 29. display-test and device id register format register data shift limit command address d7 d6 d5 d4 d3 d2 d1 d0 hex code minimum setting example (01) 0x0e 00000001 0x01 maximum setting example (83 or 0x53) 0x0e 01010011 0x53 table 30. shift-limit register format
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 26 ______________________________________________________________________________________ output map ram content address range addressed function 0 to 47 48 grids grid 0 to grid 47 48 7-segment a 14-segment a 16-segment a1 49 7-segment b 14-segment b 16-segment b 50 7-segment c 14-segment c 16-segment c 51 7-segment d 14-segment d 16-segment d2 52 7-segment e 14-segment e 16-segment e 53 7-segment f 14-segment f 16-segment f 54 7-segment g 14-segment g1 16-segment g1 55 no action 14-segment g2 16-segment g2 56 no action 14-segment h 16-segment h 57 no action 14-segment i 16-segment i 58 no action 14-segment j 16-segment j 59 no action 14-segment k 16-segment k 60 no action 14-segment l 16-segment l 61 no action 14-segment m 16-segment m 62 no action no action 16-segment a2 63 no action no action 16-segment d1 64 17 character segments digits 0 to 47 only 1st row 7-segment dp 14-segment dp 16-segment dp 65 7-segment a 14-segment a 16-segment a1 66 7-segment b 14-segment b 16-segment b 67 7-segment c 14-segment c 16-segment c 68 7-segment d 14-segment d 16-segment d2 69 7-segment e 14-segment e 16-segment e 70 7-segment f 14-segment f 16-segment f 71 7-segment g 14-segment g1 16-segment g1 72 no action 14-segment g2 16-segment g2 73 no action 14-segment h 16-segment h 74 no action 14-segment i 16-segment i 75 no action 14-segment j 16-segment j 76 no action 14-segment k 16-segment k 77 no action 14-segment l 16-segment l 78 no action 14-segment m 16-segment m 79 no action no action 16-segment a2 80 no action no action 16-segment d1 81 17 character segments digits 0 to 47 only 2nd row only valid for 96/2 mode (display mode select bit m = 1) 7-segment dp 14-segment dp 16-segment dp table 31. output map ram codes
table 33 shows how to set the output map address pointer to a value within the acceptable range. bit d7 is set to denote that the user is writing the output map address pointer. if the user attempts to set the output map address to one of the out-of-range addresses by writing data in range 0xd4 to 0xff, then address 0x00 is set instead. after the last data location 0x53 has been written, fur- ther output map data entries are ignored until the out- put map address pointer is reset. the output map data can be written to the address set by the output map address pointer. bit d7 is clear to denote that the user is writing actual output map data. the output map address pointer is autoincremented after the output map data has been written to the cur- rent location. if the user writes the output map data in the ram order, then the output map address pointer need only be set once, or even not at all as the address is set to 0x00 as power-up default (table 34). the output map data can be read by reading address 0x86. the 7-bit output map data at the address set by the output map address pointer is read back, with the msb clear. the output map address pointer is autoin- cremented after the output map data has been read from the current location, in the same way as for a write (table 35). filament drive the vfd filament is typically driven with an ac wave- form, supplied by a center-tapped 50hz or 60hz power transformer as part of the system power supply. however, if the system has only dc supplies available, the filament must be powered by a dc-to-ac or dc-to- dc converter. the MAX6850 can generate the waveforms on the phase1 and phase2 outputs to drive the vfd filament using a full bridge (push-pull drive). the phase1 and phase2 outputs can be used as general-purpose out- puts if the filament drive is not required. the bridge drive transistors are external, but the waveforms are generated by the MAX6850. the waveform generation uses pwm to set the effective rms voltage across the filament, as a fraction of the external supply voltage (figure 14) (table 36). the fila- ment switching frequency is synchronized to the multi- plex scan clock, eliminating beating artifacts due to differing filament and multiplex frequencies. the pwm duty cycle is controlled by the filament duty- cycle register (table 37). the effective rms voltage across the filament is given by the expression: v rms = filon x (v fil - v lo-bridge - v hi-bridge ) / 200 or, rearranged: duty = 200 x v rms / (v fil - v lo-bridge - v hi-bridge ) where: filon is the number to store in the filament duty-cycle register, address 0x09. v fil is the supply voltage to the filament driver bridge (v). v rms is the specified nominal filament supply voltage (v). v lo-bridge is the voltage drop across a low-side bridge driver (v). v hi-bridge is the voltage drop across a high-side bridge driver (v). MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 27 output map ram content address range addressed function 82 to 85 4 annunciators only valid for 48/1 mode (display mode select bit m = 0) annunciator a1 to annunciator a4 86 cursor cursor segment for digits 0 to 47 on 1st row 87 cursor only valid for 96/2 mode (display mode select bit m = 1) cursor segment for digits 0 to 47 on 2nd row 88 to 127 unused no action table 31. output map ram codes (continued)
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 28 ______________________________________________________________________________________ output map ram address power-up default content addressed function 0 to 39 0 to 39 (in order) grid 0 to grid 39 40 48 7-segment a 14-segment a 16-segment a1 41 49 7-segment b 14-segment b 16-segment b 42 50 7-segment c 14-segment c 16-segment c 43 51 7-segment d 14-segment d 16-segment d2 44 52 7-segment e 14-segment e 16-segment e 45 53 7-segment f 14-segment f 16-segment f 46 54 7-segment g 14-segment g1 16-segment g1 47 55 no action 14-segment g2 16-segment g2 48 56 no action 14-segment h 16-segment h 49 57 no action 14-segment i 16-segment i 50 58 no action 14-segment j 16-segment j 51 59 no action 14-segment k 16-segment k 52 60 no action 14-segment l 16-segment l 53 61 no action 14-segment m 16-segment m 54 62 no action no action 16-segment a2 55 63 no action no action 16-segment d2 56 64 7-segment dp 14-segment dp 16-segment dp 57 65 7-segment a 14-segment a 16-segment a1 58 66 7-segment b 14-segment b 16-segment b 59 67 7-segment c 14-segment c 16-segment c 60 68 7-segment d 14-segment d 16-segment d1 61 69 7-segment e 14-segment e 16-segment e 62 70 7-segment f 14-segment f 16-segment f 63 71 7-segment g 14-segment g1 16-segment g1 64 72 no action 14-segment g2 16-segment g2 65 73 no action 14-segment h 16-segment h 66 74 no action 14-segment i 16-segment i 67 75 no action 14-segment j 16-segment j 68 76 no action 14-segment k 16-segment k 69 77 no action 14-segment l 16-segment l 70 78 no action 14-segment m 16-segment m 71 79 no action no action 16-segment a2 72 80 no action no action 16-segment d1 73 81 7-segment dp 14-segment dp 16-segment dp 74 86 ( note: value is not 82.) cursor segment for digits 0 to 47 1st row 75 87 ( note: value is not 83.) cursor segment for digits 0 to 47 2nd row 76 to 83 127 no action table 32. output map ram initial power-up status
MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 29 table 35. reading output map data register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 read output map data; output map address pointer is autoincremented after the output map data has been read from the current location. 0x86 0 7 bits of output map data timing point phase1 behavior phase2 behavior example 1 duty = 1 (min) example 2 duty = 100 example 3 duty = 198 (a) low for (199 - filon) cycles low for (199 - filon) cycles 198 99 1 (b) low for (filon) cycles high for (filon) cycles 1 100 198 (c) low for (2) cycles low for (2) cycles 2 2 2 (d) high for (filon) cycles low for (filon) cycles 1 100 198 (e) low for (199 - filon) cycles low for (199 - filon) cycles 198 99 1 total 4mhz cycles (osc = 4mhz) 400 cycles = 100s 400 cycles = 100s 400 cycles = 100s 400 cycles = 100s 400 cycles = 100s table 36. filament bridge driver timing register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 set output map address to minimum (0x00) with data 0x80. (note that this address is set as a power-up default.) 0x06 1 0 0 0 0 0 0 0 set output map address to maximum 0x53 with data 0xd3. 0x06 1 1 1 1 1 0 0 1 table 33. setting output map address pointer register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 write output map data; output map address pointer is autoincremented after the output map data has been written to the current location. 0x06 0 7 bits of output map data table 34. writing output map data
MAX6850 the minimum commutation time, shown at (c) in figure 14, is set by (2/osc)s (500ns when osc = 4mhz) to ensure that shoot-through currents cannot flow during phase reversal. otherwise, the duty cycle of the bridge (total on time: total time) sets the rms voltage across the filament. this technique provides a low-cost ac fila- ment supply when using a regulated supply higher than the rms voltage rating of the filament. figure 15 shows the external components required for the filament driver using a fet bridge. phase1 and phase2 outputs phase1 and phase2 can be individually programmed as one of four output types (tables 38, 39). when using the filament drive, first ensure that the fila- ment duty-cycle register 0x09 is set to the correct value before configuring the phase1 and phase2 outputs to be filament drives. to stop the filament drive, program either phase1 or phase2 (or both) to be logic-low gen- eral-purpose outputs. both phase1 and phase2 out- puts come out of power-on-reset in logic-low condition. pump output the pump output can be programmed as one of four output types (table 40). port0 and port1 outputs port0 and port1 can be individually programmed as one of eight output types (tables 41, 42). the port1 choices are similar to the port0 choices, except that the last four items are invert logic. port0 output comes out of power-on-reset in logic-low condition, whereas port1 output initializes high. the port0 and port1 shutdown outputs allow exter- nal hardware (for example, a dc-dc converter power supply for vfd) to be disabled by the MAX6850 when the MAX6850 is shut down. the 625hz, 1250hz, and 2500hz outputs can drive a piezo sounder either from port0 or port1 alone, or by both ports together as bridge drive. for bridge drive, the sounder is connected between port0 and port1, taking advantage of the port1 output being inverted with respect to port0. select different fre- quencies for port0 and port1 to obtain a wider range of sounds when bridge drive is used. multiplex clock and blink timing the osc1 and osc2 inputs set the multiplex and blink timing for the display driver. connect an external resis- tor from osc2 to gnd and an external capacitor c osc from osc1 to gnd to set the frequency of the internal rc oscillator. alternatively, overdrive osc1 with an external ttl or cmos clock. if an exact blink rate or multiplex period is required, use an external clock ranging between 2mhz and 8mhz to drive osc1. the multiplex clock frequency determines the multiplex scan rate and the blink timing. the display scan rate is {osc / 400 / (1 + grids register value)}. there are 400 osc cycles per digit multiplex period. for example, with osc = 4mhz, each display digit is enabled for 100s. for a 40-grid display tube (grids register value = 39 or 0x27), the display scan rate is 250hz. 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 30 ______________________________________________________________________________________ (a) (b) (c) (d) (e) 100 s multiplex time period (osc = 4mhz) phase 1 phase 2 figure 14. filament bridge driver timing waveforms r2 r4 q2 q1 gnd q3 q4 phase 1 phase 2 vfil vfd tube gnd figure 15. filament bridge driver (mosfet) register data filament duty cycle command address d7 d6 d5 d4 d3 d2 d1 d0 hex code minimum setting example (01) 0x09 00000001 0x01 maximum setting example (199 or 0xc7) 0x09 11000111 0xc7 table 37. filament duty-cycle register format
the blink output is the selectable blink period clock. it is nominally 0.5hz or 1hz (osc = 4mhz). it is low dur- ing the first half of the blink period, and high during the second half. the port0 and port1 general-purpose outputs may be programmed to be blink output. synchronize the blink timing if desired by setting the t bit in the configuration register (table 21). the rc oscillator uses an external resistor r osc and an external capacitor c osc to set the oscillator fre- quency. r osc connects from osc2 to ground. c osc connects from osc1 to ground. the recommended val- ues of r osc and c osc set the oscillator to 4mhz, which makes the blink frequencies 0.5hz and 1 hz: f osc = k f / (r osc x [c osc + c stray ]) mhz where: k f = 2320 MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 31 table 38. phase1 register format register data phase1 behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. this is the power-up condition. 0x0a x x xxxx00 0xx0 general-purpose output, logic 1. 0x0a x x xxxx01 0xx1 output gives blink status: zero if blink phase p0; 1 if blink phase p1. 0x0a x x xxxx10 0xx2 filament drive phase1 (logic 0 during shutdown). 0x0a x x xxxx11 0xx3 register data phase2 behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. this is the power-up condition. 0x0b x x xxxx00 0xx0 general-purpose output, logic 1. 0x0b x x xxxx01 0xx1 output gives blink status: 0 if blink phase p0; 1 if blink phase p1. 0x0b x x xxxx10 0xx2 filament drive phase2 (logic 0 during shutdown). 0x0b x x xxxx11 0xx3 table 39. phase2 register format register data pump port behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. this is the power-up condition. 0x08 x x x x x x 0 0 0xx0 general-purpose output, logic 1. 0x08 x x x x x x 0 1 0xx1 80khz square-wave output (osc = 4mhz) (logic 0 during shutdown). 0x08 x x x x x x 1 0 0xx2 dout output. 0x08 x x x x x x 1 1 0xx3 table 40. pump register format
MAX6850 r osc = external resistor in k ? (allowable range 8k ? to 80k ? ) c osc = external capacitor in pf c stray = stray capacitance from osc1 to gnd in pf, typically 2pf for osc = 4mhz, r osc is 10k ? and c osc is 56pf. the effective value of c osc includes not only the actual external capacitor used, but also the stray capacitance from osc1 to gnd. this capacitance is usually in the 1pf to 5pf range, depending on the layout used. 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller 32 ______________________________________________________________________________________ register data port0 port behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. this is the power-up condition. 0x0c x x x x x 0 0 0 0xx0 general-purpose output, logic 1. 0x0c x x x x x 0 0 1 0xx1 outp ut g i ves b l i nk status: zer o i f b l i nk p hase p 0; 1 if blink phase p1. 0x0c x x x x x 0 1 0 0xx2 dout output. 0x0c x x x x x 0 1 1 0xx3 625hz square-wave output zero in shutdown. 0x0c x x x x x 1 0 0 0xx4 1250hz square-wave output zero in shutdown. 0x0c x x x x x 1 0 1 0xx5 2500hz square-wave output zero in shutdown. 0x0c x x x x x 1 1 0 0xx6 output gives shutdown status: zero if shutdown mode; 1 if operating mode. 0x0c x x x x x 1 1 1 0xx7 table 41. port0 register format register data port1 port behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. 0x0d x x x x x 0 0 0 0xx0 general-purpose output, logic 1. this is the power-up condition. 0x0d x x x x x 0 0 1 0xx1 output gives blink status: zero if blink phase p0; 1 if blink phase p1. 0x0d x x x x x 0 1 0 0xx2 dout output. 0x0d x x x x x 0 1 1 0xx3 inverted 625hz square-wave output 1 in shutdown. 0x0d x x x x x 1 0 0 0xx4 inverted 1250hz square-wave output 1 in shutdown. 0x0d x x x x x 1 0 1 0xx5 inverted 2500hz square-wave output 1 in shutdown. 0x0d x x x x x 1 1 0 0xx6 output gives inverted shutdown status: 1 if shutdown mode; zero if operating mode. 0x0d x x x x x 1 1 1 0xx7 table 42. port1 register format
the allowed range of f osc is 2mhz to 8mhz. if f osc is set too high, the internal oscillator can stop working. an internal fail-safe circuit monitors the multiplex clock and detects a slow or nonworking multiplex clock. when a slow or nonworking multiplex clock is detected, an internal fail-safe oscillator generates a replacement clock of about 200khz. this backup clock ensures that the vfd is not damaged by the multiplex operation halt- ing inadvertently. the scan rate for 16 digits is about 15hz in fail-safe mode, and flickers. a flickering display is a good indication that there is a problem with the multiplex clock. power supplies the MAX6850 operates from a single 2.7v to 3.6v power supply. bypass the power supply to gnd with a 0.1f capacitor as close to the device as possible. add a bulk capacitor (such as a low-cost electrolytic 1f to 22f) if the MAX6850 is driving high current from any of the general-purpose output ports. chip information transistor count: 129,898 process: cmos MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller ______________________________________________________________________________________ 33 functional diagram osc1 osc2 vfblank clk cs din dout 4-wire serial interface ram configuration registers character- generator rom output map ram user outputs filament pwm clock generator pwm brightness control vfclk vfdout vfload phase 2 phase 1 pump port 0 port 1 output shifter 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 vfclk osc2 osc1 port1 din sclk port0 gnd top view MAX6850 vfdout vfload phase1 vfblank pump phase2 v+ cs qsop pin configuration
package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) qsop.eps MAX6850 4-wire interfaced, 7-, 14-, and 16-segment alpha- numeric vacuum-fluorescent display controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 34 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products.

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